Job Description

Project description

This is a great opportunity to work as part of a highly regarded team to deliver leading-edge solutions.

Responsibilities

IP Packaging Engineer onsite at AMD Hyderabad: package, validate and release IP blocks used across chip design projects, working with design, verification and build/tooling teams. Debug multi-component flows (packaging pipelines, build flows, DV environments) to root cause, document findings and communicate status across time zones with US-based counterparts.

SKILLS

Must have

* 1 to 2 years of relevant professional experience in semiconductor design, verification, IP packaging or related domains * Working understanding of chip design fundamentals and design verification basics (RTL concepts, testbenches, simulation flows) * Demonstrated experience debugging complex systems: tracing failures across tools, scripts and design/verification/packaging flows to root cause (Python, Shell